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1、EE141 Digital Integrated Circuits2ndManufacturing1一、CMOS工艺简介；二、MOS管特性；三、Layout设计；四、估算寄生参数；五、SPICE中 MOS器件参数设置 参考书： ， EE141 Digital Integrated Circuits2ndManufacturing2Technology (Process) 三类工艺： 双极型 bipolar (三极管，二极管，电阻 ) NMOS CMOS （NMOS，PMOS）：目前主流工艺EE141 Digital Integrated Circuits2ndManufacturing3EE1
2、4129 Digital Integrated Circuits2ndIntroductionDie CostDie CostSingle dieWaferFrom http:/Going up to 12” (30cm)EE141 Digital Integrated Circuits2ndManufacturing4q芯片制造代工厂芯片制造代工厂 （Foundry）1 1） TSMC TSMC 台积电台积电 （台湾）（台湾） 可获工艺：0.5um, 0.35um, 0.25um, 0.18um, 0.13um, 0.09um 0.065um, 0.045um 2 2） CSM CSM 或称
3、或称 Chartered Chartered 新加坡特许新加坡特许 （新加坡）（新加坡） 可获工艺：0.35um, 0.25um, 0.18um, 0.13um, 0.09um, 0.065um, 0.045um 3 3） SMIC SMIC 中芯国际中芯国际 （上海）（上海） 可获工艺：可获工艺：0.350.35um, 0.25um, 0.18um, 0.13um, 0.09umum, 0.25um, 0.18um, 0.13um, 0.09um4 4）HJTCHJTC或称或称 HJ HJ 和舰科技和舰科技 ( (苏州苏州) ) 可获工艺：0.35um, 0.25um, 0.18um5 5）
4、CSMC CSMC 华润上华华润上华 （无锡）（无锡） 可获工艺：3.0至0.5微米6 6）GSMC GSMC 宏力宏力 ( (上海上海) ) 可获工艺：0.25um, 0.18um, 0.15um7 7）HHNEC HHNEC 华虹华虹 ( (上海上海) ) 可获工艺：0.35um, 0.25um, 0.18um8 8）SinoMOS SinoMOS 中纬中纬 ( (宁波宁波) ) 可获工艺：0.8um/1umEE141 Digital Integrated Circuits2ndManufacturing5q多项目晶圆服务多项目晶圆服务 多项目晶圆（多目标芯片） Multi Project
5、 Wafer - MPW多个使用相同工艺的设计，放在同一晶圆片上流片。每个设计可以得到数十片芯片样品。制造费用按照芯片面积分摊，成本仅为单独进行制造的5%-10%。 EE141 Digital Integrated Circuits2ndManufacturing6qEducational services （MPW服务机构）服务机构） 美国：MOSIS (MOS Implementation Support Project) http:/ 台湾：CIC (Chip Implementation Center) http:/www.cic.org.tw/cic_v13/main.jsp 欧盟：
6、Europractice http:/ 上海集成电路设计研究中心 http:/ 中国科学院EDA中心 http:/ EE141 Digital Integrated Circuits2ndManufacturing7MOS 管结构图: 3D PerspectiveDSGGDSDSGEE141 Digital Integrated Circuits2ndManufacturing8substraten+ n+p+substratemetal1polySiO2metal2metal3transistorviametal1insulator.多晶硅（衬底）Cross sectionEE141 Dig
7、ital Integrated Circuits2ndManufacturing9CMOS有三类工艺：EE141 Digital Integrated Circuits2ndManufacturing10EE141 Digital Integrated Circuits2ndManufacturing11p-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2EE141 Digital Integrated Circuits2ndManufacturing12VDDVDDVinVoutM1M2M3M4Vout2EE141 Di
8、gital Integrated Circuits2ndManufacturing13 1） oxidation （氧化）Si-substrate or P-type or N-typeSi-substrate or P-type or N-typeSiO2氧气SiO2 是绝缘体。是绝缘体。 它的作用是什么？它的作用是什么？EE141 Digital Integrated Circuits2ndManufacturing14SiO2 是绝缘体。是绝缘体。 它的作用是什么？它的作用是什么？EE141 Digital Integrated Circuits2ndManufacturing152）
9、Cut（光刻）(a) Photoresis (光刻胶)PhotoresistSiO2Si-substrate(d) Final result after removal of resist 去胶去胶Si-substrate(b) Exposure 曝光曝光UV-light 紫外光紫外光mask 版图版图PhotoresistSiO2(c) Etch 蚀蚀刻chemical etchPhotoresistSiO2EE141 Digital Integrated Circuits2ndManufacturing163） doping（掺杂）五阶元素五阶元素SIO2起到掩蔽作用起到掩蔽作用N-typ
10、e扩散 diffusion离子注入 ionize （现在工艺）EE141 Digital Integrated Circuits2ndManufacturing174） 连线连线：多晶硅 金属EE141 Digital Integrated Circuits2ndManufacturing18First place tubs to provide properly-doped substrate for n-type, p-type transistors:p-tubn-tubsubstrateP-well （P阱）Process steps 1: 衬底上做阱EE141 Digital Int
11、egrated Circuits2ndManufacturing19Pattern polysilicon before diffusion regions:p-tubn-tubpolypolygate oxideEE141 Digital Integrated Circuits2ndManufacturing20Add diffusions, performing self-masking:p-tubn-tubpolypolyn+n+p+p+EE141 Digital Integrated Circuits2ndManufacturing21Start adding metal layers
12、:p-tubn-tubpolypolyn+n+p+p+metal 1metal 1viasEE141 Digital Integrated Circuits2ndManufacturing22Vgs Vt : 产生反型层Vgs VTN ，VDS VTN ，VDS VGS VTN)1 ()(22DSnTNGSnnOXndVVVLWCI2)(2)(22DSDSTNGSnnoxnDSDSTNGSndVVVVLWCVVVVkIIDoxoxnOXnntCkprocess transconductance工艺跨导工艺跨导)(nnOXnnLWCkdevice transconductance器件跨导器件跨导
13、nnChannel-length modulation沟道长度调制系数沟道长度调制系数carrier mobility 电子迁移率电子迁移率COX - gate capacitance per unit area EE141 Digital Integrated Circuits2ndManufacturing26Vtn = 0.6VVtp = -0.6V)1 ()(22DSnTNGSnnOXndVVVLWCI)1 ()(22SDnTPSGppOXpdVVVLWCIIDIDThreshold voltage （以饱和区方程为例）：以饱和区方程为例）：)22(0FSBFnTNTNVVVThres
14、hold voltage for VSB=0)22(0FBSFpTPTPVVV0TNVnFBody-effect coefficientFermi potential (typical 为为 -0.3V)费米电势费米电势Bulk 调制效应，总是使有效阈值电压的绝对值增大调制效应，总是使有效阈值电压的绝对值增大一个例子 : NMOS管的VTN0 =0.68V, 当VSB =-5V时， Vt =0.16V. 有效阈值电压Vt =Vt0 + Vt=0.84VEE141 Digital Integrated Circuits2ndManufacturing27线性区线性区两端均开启两端均开启截止区截止
15、区两端均不开启两端均不开启饱和区饱和区一端开启；另一端不开启一端开启；另一端不开启（S端开启；端开启；D端不开启）端不开启）gatedrainsourcecurrentIdgatedrainsourceId源端开启源端开启Vgs Vtn漏端开启漏端开启Vgd Vtn源端开启源端开启Vgs -Vtp漏端开启漏端开启Vgd -VtpVtn = 0.6VVtp = -0.6VEE141 Digital Integrated Circuits2ndManufacturing28PolysiliconAluminum1、Layout 基本概念EE141 Digital Integrated Circui
16、ts2ndManufacturing29Masks are tooling for manufacturing 版图用于做IC.Manufacturing processes have inherent limitations in accuracy 制造工艺有精度限制.Design rules specify geometry of masks which will provide reasonable yields. 版图设计规则规定了版图的几何形状、大小等，以获得合理的成品率.Design rules are determined by experience. 版图设计规则由实验决定EE
17、141 Digital Integrated Circuits2ndManufacturing30SCMOS 是MOSIS制定的按比例缩小设计规则：基本采用按比例缩小设计规则，再加上一些限制。 1）Designed to scale across a wide range of technologies. 适用于宽广的工艺节点 2）Designed to support multiple vendors. 适用于各种制造商 3）Designed for educational use. 用于教学目的（为了方便） 4）Therefore, fairly conservative 因此，与理想的按
18、比例缩小设计规则相比，相当保守231325EE141 Digital Integrated Circuits2ndManufacturing31LayerPolyMetal1Metal2Contact To PolyContact To DiffusionViaWell (n)Active Area (p+)ColorRepresentationGreenGreenRedBlueMagentaBlackBlackBlackActive Area (n+)Yellowtub ties (p+)tub ties (n+)Well (p)Yellow2、CMOS Process Layers 工艺层
19、定义有源区(扩散层)接触孔通孔EE141 Digital Integrated Circuits2ndManufacturing32n-type 多晶硅与扩散区的交界处Poly（红）扩散区:绿:：N+黄：P+EE141 Digital Integrated Circuits2ndManufacturing33Poly（红）扩散区:黄：P+（PMOS）扩散区:绿:：N+（NMOS）Metel (上方常是电源）Metel (下方常是电源）EE141 Digital Integrated Circuits2ndManufacturing34 aoutaoutVDDVSSMetel (上方常是电源）M
20、etel (下方常是电源）PMOS通常与电源相连(在上方）NMOS通常与地相连(在上方）EE141 Digital Integrated Circuits2ndManufacturing35wL沟道长度沟道宽度电流方向W=扩散区宽度EE141 Digital Integrated Circuits2ndManufacturing36p-tubn-tubpolypolyn+n+p+p+metal 1metal 1栅氧：薄，会产生反型层场氧：厚，不会产生反型层EE141 Digital Integrated Circuits2ndManufacturing37 （Scalable Design r
21、ules）：工艺参数与版图尺寸按比例缩小 EE141 Digital Integrated Circuits2ndManufacturing381）Intra-Layer Design Rules 层内设计规则Polysilicon22Metal133Metal2432Contactor Via2Hole单位： tub tiesN+，P+221090 Well不同阱阱相同阱阱or6ActiveN+，P+3310相同扩散层扩散层不同扩散层扩散层EE141 Digital Integrated Circuits2ndManufacturing39最小宽度最小宽度 最小间距最小间距Polysilic
22、on 2 2 metal1 3 3 有源区（扩散区，有源区（扩散区，N+，P+） 3 3 Contact or Via Hole 2 2 2Contactor Via2HoleMetal133Polysilicon22ActiveN+，P+33EE141 Digital Integrated Circuits2ndManufacturing402）Inter-Layer Design Rules 层间设计规则单位： Transistors重要231325EE141 Digital Integrated Circuits2ndManufacturing41单位： W 3 最小尺寸最小尺寸L 2P
23、oly伸出有源区 2扩散层伸出poly 3Poly与有源区间距 12323115扩散层与阱边缘间距 5EE141 Digital Integrated Circuits2ndManufacturing42可获得的Contact hole and Via hole metal1/diff 接触孔 metal1/poly 接触孔 metal1/metal2 通孔 metal2/metal3 通孔4122 通孔尺寸通孔尺寸42122overlap (复盖) : 1 diff接触孔与poly间距： 2 minimum spacing(间距): 2 Cut(通孔): 2 x 2 EE141 Digita
24、l Integrated Circuits2ndManufacturing434122 尺寸尺寸 cut: 2 x 2 overlap : 1 minimum spacing: 2 阱接触与diff接触孔间距：2 2P. 81-82EE141 Digital Integrated Circuits2ndManufacturing44AAnp-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-AAAEE141 Digital Integrated Circuits2ndManufacturing45EE14
25、1 Digital Integrated Circuits2ndManufacturing46poly_not_fet to all_diff minimum spacing = 0.14 um.EE141 Digital Integrated Circuits2ndManufacturing47+baoutbaoutVDDGNDtubties4、其它单元电路版图简介EE141 Digital Integrated Circuits2ndManufacturing48baoutaboutVDDGNDtub tiesEE141 Digital Integrated Circuits2ndManu
26、facturing49inoutRL = ?CL = ?EE141 Digital Integrated Circuits2ndManufacturing50DSGBCGDCGSCSBCDBCGB复盖EE141 Digital Integrated Circuits2ndManufacturing51PolysiliconAluminumEE141 Digital Integrated Circuits2ndManufacturing52qResistance of any size square is constant 任何尺寸的方块，电阻相同R = rH WLSheet Resistanc
27、eR口 = R口 （L / W）WLHnSheet Resistance 方块电阻R1R2EE141 Digital Integrated Circuits2ndManufacturing53源/漏Parasitic ResistancesWLDDrainDraincontactPolysilicon gateDSGRSRDVGS,effWLRRRDviaD/口viaR口R通孔电阻源/漏扩散层方块电阻WLD/源/漏扩散层方块数 （spice参数，RSH）EE141 Digital Integrated Circuits2ndManufacturing54 5 20 30 5 20 寄生电阻估算
28、Poly resistivity Rpoly 4 /口 多晶硅方块电阻线弯角电阻计算（仅正方形）：0.5方块EE141 Digital Integrated Circuits2ndManufacturing55Sheet Resistance的典型数值Metal: 电阻最小多晶硅、N+、P+： 电阻大 （约50倍）各类线电阻比较EE141 Digital Integrated Circuits2ndManufacturing56substrate1） Poly/metal线-衬底电容 Two components （两部分）: parallel plate （平板电容） Fringe （边缘电
29、容）.Metal / ployfringeplateEE141 Digital Integrated Circuits2ndManufacturing57DielectricSubstrateLWHtdiElectrical-field linesCurrent flowSCWLtcplatedidi1（1）parallel plate （平板电容）plateC单位面积平板电容S平板面积EE141 Digital Integrated Circuits2ndManufacturing58（2）Fringe （边缘电容）LCcfringe2SubstrateL边缘电容2CCC1EE141 Dig
30、ital Integrated Circuits2ndManufacturing59qCan couple to adjacent wires on above/below layers 不同层之间耦合电容 metal 2metal 1metal 1SCcmm32, 12, 1 mmCS单位面积m1与m2耦合电容m1与m2复盖面积3cnCan couple to adjacent wires on same layer 同一层之间耦合电容 xlCcmm1, 14 x4cEE141 Digital Integrated Circuits2ndManufacturing603、Diffusion
31、capacitance formed by p-n junctions （P-N结扩散电容）depletion region耗尽层n+ (ND)substrate (NA)bottomwallCapacitance底部电容sidewallCapacitances侧壁电容EE141 Digital Integrated Circuits2ndManufacturing61CJSW= CJSW0 (1 + Vr/Vbi) msw CJSW0 zero-bias sidewall capacitance (零偏压侧壁电容) （SPICE参数） msw sidewall grading coeffic
32、ient ( 侧壁电容梯度系数) （SPICE参数） 若突变结（abrupt junction）, msw = - Vr voltage across the junction (P-N 结反偏电压) Vbi built-in voltage （ P -N 结内建电势） Vbi = (k*T/q) ln(NAND/ni2) 1） Sidewall capacitances 侧壁电容n+ (ND)substrate (NA)EE141 Digital Integrated Circuits2ndManufacturing62CJ= CJ0 (1 + Vr/Vbi) m CJ0 zero-bias
33、 bottomwall capacitance (零偏压底部电容) （SPICE） m bottomwall grading coefficient (底部电容梯度系数) （SPICE） 若突变结（abrupt junction）, m = - Vr voltage across the junction (P-N 结反偏电压) Vbi built-in voltage （ P -N 结内建电势） Vbi = (k*T/q) ln(NAND/ni2) 2） bottomwall capacitance 底部电容n+ (ND)substrate (NA)EE141 Digital Integra
34、ted Circuits2ndManufacturing630.12u各类线电容比较Metal: 电容最小多晶硅： 电容也较小N+、P+： 电容大 （十倍以上） EE141 Digital Integrated Circuits2ndManufacturing64各类线电容、电阻比较 线线 电容电容 电阻电阻 线性能线性能 用途用途Metal 最小 最小 好 各类线 多晶硅 较小 大 （约50倍） 中 局部连线N+、P+ 大 （约十倍） 大 （约50倍） 差 MOS管内部线（重要）EE141 Digital Integrated Circuits2ndManufacturing65qGate
35、to substrate 栅-衬底电容 CGBqgate to source/drain overlap capacitances 栅源/漏电复盖电容 CGS CGDqSource/drain diffusion capacitance源/漏扩散电容 CSB CDBDSGBCGDCGSCSBCDBCGB复盖EE141 Digital Integrated Circuits2ndManufacturing661）Gate capacitance 栅电容 CG = Cox WLCox is gate capacitor per unit area (单位面积栅电容)toxn+n+Cross sec
36、tionLGate oxidexdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WCox = ox / xoxox = 3.46 x 10-13 F/cm2Permittivity（介电常数）of siliconXox is oxide thichness (栅氧厚度) (SPICE中用tox表示Xox) p.66CGB = CGEE141 Digital Integrated Circuits2ndManufacturing672） Source/drain overlap capacitances Cgs, Cgd.
37、Determined by source/gate and drain/gate overlaps. Independent of transistor L. Cgs = Col WCol 每单位宽度复盖电容CGBOCGSOCGDOSPICE 参数 P.66xdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WEE141 Digital Integrated Circuits2ndManufacturing683） Source/drain diffusion capacitance.源/漏扩散电容 CSB CDBDSGBC
38、GDCGSCSBCDBCGBEE141 Digital Integrated Circuits2ndManufacturing69五、 MOS器件SPICE参数设置 在SPICE仿真中： 线电阻：可不计 金属、多晶硅线电容：应估算，写入网表中 MOS管电容：不应写入网表中，但要按版图给出相应的参数 在手工理论分析中：上述所有寄生电容均应计入 EE141 Digital Integrated Circuits2ndManufacturing702EE141 Digital Integrated Circuits2ndManufacturing712EE141 Digital Integrated Circuits2ndManufacturing7220
