Turbo码编译码系统设计及其FPGA实现

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1、精选优质文档-倾情为你奉上硕 士 学 位 论 文题目 Turbo码编/译码系统设计及其FPGA实现 （英文） The Design of Turbo Coding / Decoding System and its Implement with FPGA 专心-专注-专业摘 要Turbo码的出现是纠错编码史上的一个重大突破，它具有在低信噪比下接近Shannon理论极限的优异译码性能，在许多通信系统中都有很大的应用前景。本文主要研究的是Turbo码的编码和译码算法及其FPGA硬件实现。首先，介绍了课题的研究背景和Turbo译码的国内外研究现状；其次在介绍Turbo编译码原理的基础上对目前常用的各

2、类译码算法进行介绍和性能分析；接着主要研究Turbo码译码器的设计，最后用硬件实现了其电路。本文分别对Turbo码的MAP算法，Max-Log-MAP算法，Log-MAP算法、SOVA算法等进行了推导。在深入分析译码算法的基础上，决定采用Log-MAP算法作为本系统的译码算法。在对该系统的硬件实现过程中，为了节约硬件资源和减少延时，对Log-MAP算法进行了一些改进。在系统设计中，根据FPGA技术的优点，采用“自上而下”和“自下而上”结合的设计方法，通过适当的模块分割，将Turbo码的译码器分为三大模块: Log-MAP译码单元模块、交织/解交织器模块和控制信号产生模块。本文针对编码器中的延时

3、模块采用一种类似于交织器的方式来实现延时功能，使其精度更高，编码效果更好。并对译码器进行了研究，给出了一种查找表法来实现复杂的E函数，此方法明显的简化了系统的运算复杂度。在硬件实现Log-MAP算法过程中，通过巧妙地改变前向矢量的计算顺序，减少了系统占用的硬件资源。最后利用Quartus II软件对编译码系统做了计算机仿真，结果表明本系统实现的Turbo码译码器的误码性能较好，具有一定的实用价值。关键词: Turbo码， Log-MAP算法， 软判决， FPGAABSTRACTThe emergence of Turbo-Code is considered as the most excit

4、ing and potentially important development in the history of error-correcting codes. It has a superior decoding performance approaching the Shannon limit and has been widely applicated in many communication systems. The goal of this paper is to study Turbo encoding/decoding algorithm and its hardware

5、 implementation with FPGA. Firstly, it introduces background of the subject and the research situation about Turbo decoding; Secondly, it introduces the current various decoding algorithm and analyzes their performance respectively based on analyzing the encoding / decoding principle of Turbo-Code;

6、then studies the design of the Turbo decoder which hardware circle is successfully implemented finally. Including the MAP algorithm, Max-Log-MAP algorithm, Log-MAP algorithm and SOVA algorithm in Turbo-Code algorithm is deduced respectively in the paper. On the base of in-depth analysis of the decod

7、ing algorithm, the Log-MAP algorithm as the decoding algorithm in the system is selected. In the realization process of hardware in this system, Log-MAP algorithm has been improved in order to save the hardware resources and reduce delay. In the design of Turbo-Code system, the combining design meth

8、od of both from top to bottom and from bottom to top is implemented according to advantage of the FPGA, and the decoder is divided into three blocks: Log-MAP decoder, interleaver / deinterleaver block and timing control block, through appropriate segmentation module.In this paper, a similar interlea

9、ver is used by the delay module of the encoder as an approach to achieve delay function, which makes it more precise, effective and better. Meanwhile, in the study of the decoder, a look-up table method is given to achieve complex E-function, and the method significantly simplifies operation complex

10、ity of the system. In the process of the Log-MAP algorithm implementation with hardware, the calculation of vector sequence is subtly changed, which can reduce the share of the hardware resources. Finally, encoding/decoding system is simulated by the Quartus II software, and the result shows that Tu

11、rbo-Code system has a better error performance and some practical value.Key Words: Turbo Codes, Log-MAP Algorithm, Soft Decision,Field Programmable Gate Array目 录第一章 绪论Turbo码的提出对信道编码领域的研究有着重要的意义。由于Turbo码具有接近Shanon理论极限的性能1，尤其是低信噪比下的优异性能使Turbo码在许多通信系统中都有非常大的应用潜力。除了在深空通信、卫星通信以及多媒体通信等领域的应用外，Turbo码在无线移动通信