The BTeV Pixel Detector该btev像素探测器.ppt

The BTeV Pixel Detector该btev像素探测器
BTeV
30 Station
Pixel Detector (in vacuum)
page 2
BTeV Context
BTeV philosophy:
Achieve best B sensitivity by triggering on separated vertex (reconstructable B event)
Two enabling technologies:
Pixel detector with fast readout
Very low occupancy = “trivial” track finding
Data driven pipelined track and vertex processor
page 3
Key Early Technology Decision
Hybrid silicon pixel detectors
Allows separate optimization of sensor & readout chip
Rely on LHC R&D for sensor R&D
BTeV sensors are oxygenated n-in-n with moderated p-spray isolation (essentially a copy of the ATLAS pixel sensors)
Concentrate on ROC and mechanical design
page 4
Other key technology choices
Carbon fiber reinforced TPG (Thermal Paralytic Graphite) heat spreader/mechanical support
Considered CVD diamond, but rejected because flatness is problematic
LN2 cooling
Minimum number of cooling pipes, no joints in vacuum
Also required for vacuum (cryo-pumping)
Solder bump bonding
page 5
Readout ASIC design
Readout speed requirement drove everything
Minimal data loss in sensor 6mm from beam line with 45MHz interaction rate
Secondary requirements:
Good spatial resolution (<10m)
Achievable with moderate pixel size and very coarse pulse height measurement (Artuso & Wang)
Time stamped by beam crossing (132ns  396ns)
Relaxed time walk requirement (wrt LHC) allowed use of a single discriminator threshold per chip
page 6
ASIC technology choice
Originally aimed at Honeywell 0.5m SOI CMOS
Quickly (2019) started testing deep submicron CMOS after initial CERN results.
Primary radiation damage mechanism is charge trapping in oxide (causes transistor threshold shift and formation of parasitic channels)
Quantum mechanics to the rescue
Small feature size  thin oxide  Quantum tunneling
0.25m CMOS can be made radiation tolerant by using enclosed geometry transistors and guard rings
(0.13m CMOS probably doesn’t require enclosed geometry transistors)
page 7